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SH7101 Datasheet(PDF) 65 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 65 Page - Renesas Technology Corp |
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65 / 560 page ![]() Section 2 CPU Rev.1.00 Sep. 18, 2008 Page 31 of 522 REJ09B0069-0100 Classification Types Operation Code Function No. of Instructions 11 CLRT T bit clear 31 System control CLRMAC MAC register clear LDC Load to control register LDS Load to system register NOP No operation RTE Return from exception processing SETT T bit set SLEEP Transition to power-down mode STC Store control register data STS Store system register data TRAPA Trap exception handling Total: 62 142 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. |
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