SH7101 datasheet(100/560 Pages) RENESAS

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Section 5 Exception Processing

Rev.1.00 Sep. 18, 2008 Page 66 of 522

REJ09B0069-0100

5.3.2

Address Error Exception Processing

When an address error occurs, the bus cycle in which the address error occurred ends, the current

instruction finishes, and then address error exception processing starts. The CPU operates as

follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

3. The start address of the exception service routine is fetched from the exception processing

vector table that corresponds to the occurred address error, and the program starts executing

from that address. The jump in this case is not a delayed branch.

5.4

Interrupts

5.4.1

Interrupt Sources

Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, IRQ, and

on-chip peripheral modules.

Table 5.7

Interrupt Sources

Type

Request Source

Number of Sources

NMI

NMI pin (external input)

IRQ

IRQ0 to IRQ3 pins (external input)

On-chip peripheral module

Multifunction timer pulse unit

Compare match timer

A/D converter (A/D0 and A/D1)

A/D converter (A/D2)

Serial communication interface

Watchdog timer

Motor management timer

Input/output port

Each interrupt source is allocated a different vector number and vector table offset. See section 6,

Interrupt Controller (INTC), and table 6.2, Interrupt Exception Sources, Vector Addresses and

Priorities, for more information on vector numbers and vector table address offsets.

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