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SH7101 Datasheet(PDF) 103 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 103 Page - Renesas Technology Corp |
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103 / 560 page ![]() Section 5 Exception Processing Rev.1.00 Sep. 18, 2008 Page 69 of 522 REJ09B0069-0100 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. 5.6 Cases when Exception Sources Are Not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. In this case, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Address Error Interrupt Immediately after a delayed branch instruction* 1 Not accepted Not accepted Immediately after an interrupt-disabled instruction* 2 Accepted Not accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 5.6.1 Immediately after a Delayed Branch Instruction When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction placed immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction When an instruction placed immediately after an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors can be accepted. |
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