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SH7101 Datasheet(PDF) 53 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 53 Page - Renesas Technology Corp |
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53 / 560 page ![]() Section 2 CPU Rev.1.00 Sep. 18, 2008 Page 19 of 522 REJ09B0069-0100 2.3 Data Formats 2.3.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 Longword Figure 2.2 Data Format in Registers 2.3.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. 31 0 15 23 7 Byte Byte Byte Byte Word Word Address 2n Address 4n Longword Address m Address m + 2 Address m + 1 Address m + 3 Figure 2.3 Data Formats in Memory 2.3.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. |
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