SH7101 datasheet(73/560 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Sep. 18, 2008 Page 39 of 522

REJ09B0069-0100

Branch Instructions

Table 2.16

Branch Instructions

Instruction

Instruction Code

Operation

Execu-

tion

States

T Bit

label

10001011dddddddd

If T = 0, disp

× 2 + PC → PC; if T =

1, nop

3/1*

—

BF/S

label

10001111dddddddd

Delayed branch, if T = 0, disp

× 2 +

→ PC; if T = 1, nop

3/1*

—

label

10001001dddddddd

If T = 1, disp

× 2 + PC → PC; if T =

0, nop

3/1*

—

BT/S

label

10001101dddddddd

Delayed branch, if T = 1, disp

× 2 +

→ PC; if T = 0, nop

2/1*

—

BRA

label

1010dddddddddddd

Delayed branch, disp

× 2 + PC →

—

BRAF

0000mmmm00100011

Delayed branch, Rm + PC

→ PC

—

BSR

label

1011dddddddddddd

Delayed branch, PC

→ PR, disp × 2

+ PC

→ PC

—

BSRF

0000mmmm00000011

Delayed branch, PC

→ PR,

Rm + PC

→ PC

—

JMP

@Rm

0100mmmm00101011

Delayed branch, Rm

→ PC

—

JSR

@Rm

0100mmmm00001011

Delayed branch, PC

→ PR,

→ PC

—

RTS

0000000000001011

Delayed branch, PR

→ PC

—

Note:

One state when the program does not branch.

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