SH7101 datasheet(99/560 Pages) RENESAS

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Section 5 Exception Processing

Rev.1.00 Sep. 18, 2008 Page 65 of 522

REJ09B0069-0100

5.3

Address Errors

5.3.1

The Cause of Address Error Exception

Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6.

Table 5.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus Master

Bus Cycle Description

Address Errors

Instruction fetched from even address

None (normal)

Instruction fetched from odd address

Address error occurs

Instruction fetched from other than on-chip

peripheral module space*

None (normal)

Instruction fetched from on-chip peripheral

module space*

Address error occurs

Instruction

fetch

CPU

Instruction fetched from external memory

space when in single chip mode

Address error occurs

Word data accessed from even address

None (normal)

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Data

read/write

CPU

Longword data accessed from other than a

long-word boundary

Address error occurs

Byte or word data accessed in on-chip

peripheral module space*

None (normal)

Longword data accessed in 16-bit on-chip

peripheral module space*

None (normal)

Longword data accessed in 8-bit on-chip

peripheral module space*

Address error occurs

External memory space accessed when in

single chip mode

Address error occurs

Note:

See section 7, Bus State Controller (BSC) for more information on the on-chip

peripheral module space.

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