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SH7101 Datasheet(PDF) 57 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 57 Page - Renesas Technology Corp

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Section 2 CPU
Rev.1.00 Sep. 18, 2008 Page 23 of 522
REJ09B0069-0100
Table 2.8
Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Direct register
addressing
Rn
The effective address is register Rn. (The operand
is the contents of register Rn.)
—
Indirect register
addressing
@Rn
The effective address is the contents of register
Rn.
Rn
Rn
Rn
Post-increment
indirect register
addressing
@Rn+
The effective address is the contents of register
Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
1/2/4
+
Rn + 1/2/4
Rn
(After the
instruction
executes)
Byte:
Rn + 1
→ Rn
Word:
Rn + 2
→ Rn
Longword:
Rn + 4
→ Rn
Pre-decrement
indirect register
addressing
@-Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
1/2/4
Rn – 1/2/4
–
Rn – 1/2/4
Byte:
Rn – 1
→ Rn
Word:
Rn – 2
→ Rn
Longword:
Rn – 4
→ Rn
(Instruction is
executed with
Rn after this
calculation)
Indirect register
addressing with
displacement
@(disp:4,
Rn)
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
Rn + disp
× 1/2/4
+
×
1/2/4
disp
(zero-extended)
Byte:
Rn + disp
Word:
Rn + disp
× 2
Longword:
Rn + disp
× 4



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