SH7101 datasheet(76/560 Pages) RENESAS

76 / 560 page

Section 2 CPU

Rev.1.00 Sep. 18, 2008 Page 42 of 522

REJ09B0069-0100

2.6

Processing States

2.6.1

State Transitions

The CPU has five processing states: reset, exception processing, bus release, program execution,

and power-down. Figure 2.4 shows the transitions between the states.

From nay state

when

= 0

and

From nay state when

= 0,

and

= 0

= 1

= 1,

= 1

Power-on reset state

Manual reset state

Bus release state

Sleep mode

Program execution state

Hardware standby mode

Software standby mode

Exception

processing state

When an internal power-on

reset by WDT or internal

manual reset by

WDT occurs

Bus request

generated

Bus request

released

Bus request

generated

Bus request

released

SSBY bit cleared

for SLEEP

instruction

SSBY bit set

for SLEEP

instruction

Power-down mode

From any state when

= 0 and

= 0

Exception

processing

endws

Exception

processing

source

occurs

Bus request

released

Bus request

released

Reset state

= 0

= 1

Figure 2.4 Transitions between Processing States

Reset State: The CPU resets in the reset state. When the

RES pin level goes low, the power-on

reset state is entered. When the

RES pin is high and the MRES pin is low, the manual reset state is

entered. When the

HSTBY pin is driven high and the RES pin level goes low, the power-on reset

state is entered.

Exception Processing State: The exception processing state is a transient state that occurs when

exception processing sources such as resets or interrupts alter the CPU’s processing state flow.

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