SH7101 datasheet(91/560 Pages) RENESAS

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Section 4 Clock Pulse Generator

Rev.1.00 Sep. 18, 2008 Page 57 of 522

REJ09B0069-0100

EXTAL

XTAL

External clock input

Open state

Figure 4.4 Example of External Clock Connection

4.2

Function for Detecting the Oscillator Halt

This CPG can detect a clock halt and automatically cause the timer pins to become high-

impedance when any system abnormality causes the oscillator to halt. That is, when a change of

EXTAL has not been detected, the high-current 12 pins (PE9/TIOC3B, PE11/TIOC3D,

PE12/TIOC4A, PE13/TIOC4B/

MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT, PE16/PUOA,

PE17/PVOA, PE18/PWOA, PE19/PUOB, PE20/PVOB, PE21/PWOB) are set to high-impedance

regardless of PFC setting.

Even in standby mode, these 12 pins become high-impedance regardless of PFC setting. These

pins enter the normal state after standby mode is released. When abnormalities that halt the

oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI

operations, including these 12 pins, become undefined even when the oscillator operation starts

again.

4.3

Usage Notes

4.3.1

Note on Crystal Resonator

A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator

connection examples shown in this section, because various characteristics related to the crystal

resonator are closely linked to the user’s board design. Since the resonator circuit component

values depend on the resonator itself, floating capacitances in the application circuit, and other

factors, we recommend consulting with the resonator manufacturer to determine the circuit

component values used. Ensure that a voltage exceeding the maximum rating is not applied to the

oscillator pin.

4.3.2

Notes on Board Design

Measures against radiation noise are taken in this LSI. If radiation noise needs to be further

reduced, usage of a multi-layer printed circuit board with ground planes is recommended.

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