SH7101 datasheet(96/560 Pages) RENESAS

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Section 5 Exception Processing

Rev.1.00 Sep. 18, 2008 Page 62 of 522

REJ09B0069-0100

Exception Sources

Vector Numbers

Vector Table Address Offset

IRQ0

H'00000100 to H'00000103

IRQ1

H'00000104 to H'00000107

IRQ2

H'00000108 to H'0000010B

IRQ3

H'0000010C to H'0000010F

H'00000110 to H'00000113

H'00000114 to H'00000117

H'00000118 to H'0000011B

Interrupts

Reserved by system

H'0000011C to H'0000011F

On-chip peripheral module*

255

H'00000120 to H'00000123

H'000003FC to H'000003FF

Note:

The vector numbers and vector table address offsets for each on-chip peripheral

module interrupt are given in section 6, Interrupt Controller, and table 6.2, Interrupt

Exception Sources, Vector Addresses and Priorities.

Table 5.4

Calculating Exception Processing Vector Table Addresses

Exception Source

Vector Table Address Calculation

Resets

Vector table address = (vector table address offset)

= (vector number)

× 4

Address errors, interrupts,

instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Notes: 1. VBR: Vector base register

2. Vector table address offset: See table 5.3.

3. Vector number: See table 5.3.

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