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SH7101 Datasheet(PDF) 75 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 560 page  Section 2 CPU Rev.1.00 Sep. 18, 2008 Page 41 of 522 REJ09B0069-0100 Instruction Instruction Code Operation Execu- tion States T Bit STS.L MACL,@–Rn 0100nnnn00010010 Rn – 4 → Rn, MACL → (Rn) 1 — STS.L PR,@–Rn 0100nnnn00100010 Rn – 4 → Rn, PR → (Rn) 1 — TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm × 4 + VBR) → PC 8 — Note: * The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) equals to the register used by the next instruction. |
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