SH7101 datasheet(237/560 Pages) RENESAS

237 / 560 page

Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 203 of 522

REJ09B0069-0100

ca d

T2 period

T1 period

TGRA_3

TCDR

TDDR

H'0000

Positive phase

Negative phase

Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)

Complementary PWM Mode 0% and 100% Duty Cycle Output: In complementary PWM

mode, 0% and 100% duty cycles can be output as required. Figures 8.43 to 8.47 show output

examples.

100% duty cycle output is performed when the data register value is set to H'0000. The waveform

in this case has a positive phase with a 100% on-state. 0% duty cycle output is performed when

the data register value is set to the same value as TGRA_3. The waveform in this case has a

positive phase with a 100% off-state.

On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off

compare-match for the same phase occur simultaneously, both compare-matches are ignored and

the waveform does not change.

Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output

can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in

the timer output control register (TOCR). An example of a toggle output waveform is shown in

figure 8.48.

This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match

between TCNT4 and H'0000.

SH7101 Datasheet(PDF) 237 Page - Renesas Technology Corp