SH7785 datasheet(37/1692 Pages) RENESAS

37 / 1692 page

1. Overview

Rev.1.00 Jan. 10, 2008 Page 7 of 1658

REJ09B0261-0100

Item

Features

DDR2-SDRAM bus

controller (DBSC)

• A dedicated DDR2-SDRAM bus interface

⎯ Multi-bank support: Supports multi-bank (four banks) operation

⎯ Number of banks: Supports four or eight banks (however, no more

than four banks can be opened concurrently)

⎯ Selectable bus width: 32-/16-bit

⎯ Supports preceding precharging and activation

⎯ Burst length: Four (fixed)

⎯ Burst type: Sequential (fixed)

⎯ CAS latency: 2, 3, 4, 5, 6 cycles

• Auto-refresh mode

⎯ An average interval is selectable by a register setting. Preceding

refresh operations are performed when there are no pending

requests.

• Self-refresh mode

• Connectable memory capacity: Up to 1 Gbyte

⎯ With a 32-bit bus width

16 M x 16 bits (256 Mbits) x 2, 32 M x 16 bits (512 Mbits) x 2, 64 M x

16 bits (1 Gbit) x 2, 128 M x 16 bits (2 Gbits) x 2, 32 M x 8 bits (256

Mbits) x 4, 64 M x 8 bits (512 Mbits) x 4, 128 M x 8 bits (1 Gbit) x 4,

256 M x 8 bits (2 Gbits) x 4

⎯ With a 16-bit bus width

16 M x 16 bits (256 Mbits) x 1, 32 M x 16 bits (512 Mbits) x 1, 64 M x

16 bits (1 Gbit) x 1, 128 M x 16 bits (2 Gbits) x 1, 32 M x 8 bits (256

Mbits) x 2, 64 M x 8 bits (512 Mbits) x 2, 128 M x 8 bits (1 Gbit) x 2,

256 M x 8 bits (2 Gbits) x 2

• Big or little endian is selectable

SH7785 Datasheet(PDF) 37 Page - Renesas Technology Corp