SH7785 datasheet(82/1692 Pages) RENESAS

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3. Instruction Set

Rev.1.00 Jan. 10, 2008 Page 52 of 1658

REJ09B0261-0100

3.3

Instruction Set

Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13.

Table 3.3

Notation Used in Instruction List

Item

Format

Description

Instruction

mnemonic

OP.Sz SRC, DEST

OP:

Operation code

Sz:

Size

SRC:

Source operand

DEST:

Source and/or destination operand

Rm:

Source register

Rn:

Destination register

imm:

Immediate data

disp:

Displacement

Operation

notation

→, ←

Transfer direction

(xx)

Memory operand

M/Q/T

SR flag bits

Logical AND of individual bits

Logical OR of individual bits

∧

Logical exclusive-OR of individual bits

Logical NOT of individual bits

<<n, >>n n-bit shift

Instruction code

MSB

↔ LSB

mmmm: Register number (Rm, FRm)

nnnn:

0000:

R0, FR0

0001:

R1, FR1

1111:

R15, FR15

mmm:

nnn:

000:

DR0, XD0, R0_BANK

001:

DR2, XD2, R1_BANK

111:

DR14, XD14, R7_BANK

mm:

nn:

00:

FV0

01:

FV4

10:

FV8

11:

FV12

iiii:

Immediate data

dddd:

Displacement

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