SH7785 datasheet(31/1692 Pages) RENESAS

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1. Overview

Rev.1.00 Jan. 10, 2008 Page 1 of 1658

REJ09B0261-0100

Section 1 Overview

The SH7785 incorporates a DDR2-SDRAM interface, a PCI controller, a DMA controller, timers,

serial interfaces, audio interfaces, a graphics data translation accelerator (GDTA) that supports

YUV data conversion and motion compensation processing, and a display unit (DU) that supports

digital RGB display. The DDR2 interface, PCI interface, and the local bus are independent,

providing dedicated external bus interfaces for the transfer of large amounts of data and of

streaming data.

The SH7785 contains an SH-4A (PVR.VER = H'30: Extended version), which is a 32-bit RISC

(reduced instruction set computer) multiprocessor including an FPU as well as a CPU, providing

upward compatibility (instruction set level) with the SH-1, SH-2, SH-3, and SH-4

microcomputers. The CPU and FPU run at 600 MHz. The processor also includes an instruction

cache, an operand cache for which copy-back or write-through mode is selectable, a four-entry

fully associative instruction TLB (translation look-aside buffer), and an MMU (memory

management unit) with a 64-entry fully associative unified TLB.

1.1

Features of the SH7785

The features of the SH7785 are listed in table 1.1

Table 1.1

SH7785 Features

Item

Features

LSI

• CPU Operating frequency: 600 MHz

• Voltage: 1.1 V (internal), 1.8 V (DDR2-SDRAM), 3.3 V (I/O)

• Package: 436-pin BGA (size: 19 × 19 mm, pin pitch: 0.8 mm)

• External bus (local bus)

⎯ Separate 26-bit address and 64-bit data buses (the PCI bus is not

available when the 64-bit data bus is in use)

⎯ External bus frequency: up to 100 MHz

• External bus (DDR2-SDRAM bus interface)

⎯ Separate 15-bit address and 32-bit data buses

⎯ External bus frequency: up to 300 MHz (600 Mbps)

• External bus (PCI bus):

⎯ 32-bit address/data multiplexed bus

⎯ External bus frequency: 33 MHz or 66 MHz

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