SH7785 datasheet(76/1692 Pages) RENESAS

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3. Instruction Set

Rev.1.00 Jan. 10, 2008 Page 46 of 1658

REJ09B0261-0100

Table 3.1

Execution Order of Delayed Branch Instructions

Instructions

Execution Order

BRA

TARGET

(Delayed branch instruction)

BRA

ADD

(Delay slot)

↓

ADD

↓

TARGET

target-inst

(Branch destination instruction)

target-inst

A slot illegal instruction exception may occur when a specific instruction is executed in a delay

slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for

which the branch is not taken is also a delay slot instruction.

(5)

T Bit

The T bit in SR is used to show the result of a compare operation, and is referenced by a

conditional branch instruction. An example of the use of a conditional branch instruction is shown

below.

ADD

#1, R0

; T bit is not changed by ADD operation

CMP/EQ R1, R0

; If R0 = R1, T bit is set to 1

TARGET

; Branches to TARGET if T bit = 1 (R0 = R1)

In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is

used before modification, and in data access, the MD bit is accessed after modification. The other

bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction

execution. The STC and STC.L SR instructions access all SR bits after modification.

(6)

Constant Values

An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit

and 32-bit constant values can be defined as literal constant values in memory, and can be

referenced by a PC-relative load instruction.

MOV.W

@(disp, PC), Rn

MOV.L

@(disp, PC), Rn

There are no PC-relative load instructions for floating-point operations. However, it is possible to

set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point

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