SH7785 datasheet(64/1692 Pages) RENESAS

64 / 1692 page

2. Programming Model

Rev.1.00 Jan. 10, 2008 Page 34 of 1658

REJ09B0261-0100

Bit

Bit Name

Initial

Value

R/W

Description

27 to 16 —

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

R/W

FPU Disable Bit

When this bit is set to 1 and an FPU instruction is not in

a delay slot, a general FPU disable exception occurs.

When this bit is set to 1 and an FPU instruction is in a

delay slot, a slot FPU disable exception occurs. (FPU

instructions: H'F*** instructions and LDS (.L)/STS(.L)

instructions using FPUL/FPSCR)

14 to 10 —

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

R/W

M Bit

Used by the DIV0S, DIV0U, and DIV1 instructions.

R/W

Q Bit

Used by the DIV0S, DIV0U, and DIV1 instructions.

7 to 4

IMASK

1111

R/W

Interrupt Mask Level Bits

An interrupt whose priority is equal to or less than the

value of the IMASK bits is masked. It can be chosen by

CPU operation mode register (CPUOPM) whether the

level of IMASK is changed to accept an interrupt or not

when an interrupt is occurred. For details, see appendix

A, CPU Operation Mode Register (CPUOPM).

3, 2

—

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

R/W

S Bit

Used by the MAC instruction.

R/W

T Bit

Indicates true/false condition, carry/borrow, or

overflow/underflow.

For details, see section 3, Instruction Set.

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