SH7785 datasheet(22/1692 Pages) RENESAS

22 / 1692 page

Rev.1.00 Jan. 10, 2008 Page xxii of xxx

REJ09B0261-0100

20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000

20.3.22 MC Status Register (MCSR) ............................................................................ 1003

20.3.23 MC Frame Width Setting Register (MCWR) ................................................... 1004

20.3.24 MC Frame Height Setting Register (MCHR) ................................................... 1005

20.3.25 MC Y Padding Size Setting Register (MCYPR) .............................................. 1006

20.3.26 MC UV Padding Size Setting Register (MCUVPR) ........................................ 1007

20.3.27 MC Output Frame Y Pointer Register (MCOYPR).......................................... 1008

20.3.28 MC Output Frame U Pointer Register (MCOUPR).......................................... 1008

20.3.29 MC Output Frame V Pointer Register (MCOVPR).......................................... 1009

20.3.30 MC Past Frame Y Pointer Register (MCPYPR)............................................... 1009

20.3.31 MC Past Frame U Pointer Register (MCPUPR)............................................... 1010

20.3.32 MC Past Frame V Pointer Register (MCPVPR)............................................... 1010

20.3.33 MC Future Frame Y Pointer Register (MCFYPR) ........................................... 1011

20.3.34 MC Future Frame U Pointer Register (MCFUPR) ........................................... 1011

20.3.35 MC Future Frame V Pointer Register (MCFVPR) ........................................... 1012

20.4

GDTA Operation ............................................................................................................. 1013

20.4.1

Explanation of CL Operation............................................................................ 1013

20.4.2

Explanation of MC Operation........................................................................... 1019

20.5

Interrupt Processing ......................................................................................................... 1029

20.6

Data Alignment................................................................................................................ 1029

20.7

Usage Notes ..................................................................................................................... 1031

20.7.1

Regarding Module Stoppage ............................................................................ 1031

20.7.2

Regarding Deep Sleep Modes........................................................................... 1031

20.7.3

Regarding Frequency Changes ......................................................................... 1032

Section 21 Serial Communication Interface with FIFO (SCIF) ........................... 1033

21.1

Features............................................................................................................................ 1033

21.2

Input/Output Pins............................................................................................................. 1039

21.3

Register Descriptions ....................................................................................................... 1040

21.3.1

Receive Shift Register (SCRSR) ...................................................................... 1046

21.3.2

Receive FIFO Data Register (SCFRDR) .......................................................... 1046

21.3.3

Transmit Shift Register (SCTSR) ..................................................................... 1047

21.3.4

Transmit FIFO Data Register (SCFTDR)......................................................... 1047

21.3.5

Serial Mode Register (SCSMR) ....................................................................... 1048

21.3.6

Serial Control Register (SCSCR) ..................................................................... 1051

21.3.7

Serial Status Register n (SCFSR) ..................................................................... 1055

21.3.8

Bit Rate Register n (SCBRR) ........................................................................... 1061

21.3.9

FIFO Control Register n (SCFCR) ................................................................... 1062

21.3.10 Transmit FIFO Data Count Register n (SCTFDR) ........................................... 1064

21.3.11 Receive FIFO Data Count Register n (SCRFDR) ............................................ 1065

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