SH7785 datasheet(41/1692 Pages) RENESAS

41 / 1692 page

1. Overview

Rev.1.00 Jan. 10, 2008 Page 11 of 1658

REJ09B0261-0100

Item

Features

Synchronized serial

I/O with FIFO

(SIOF)

• Number of channels: One (max.)

• Supports full-duplex operation

• Separate 64-byte (32 bits x 16) FIFOs for transmission and reception

• Supports the input and output of 8-/16-bit monaural and 16-bit

stereophonic audio data

• Method of synchronization selectable as frame synchronization pulses or

left/right channel switching

• Allows connection of linear, audio, A-law, or μ-Law CODEC chip

• Select an on-chip peripheral clock or input on an external pin as base for

the sampling-rate clock

• Maximum sampling rate: 48 kHz

• On-chip prescaler that uses the on-chip peripheral clock

Serial protocol

interface (HSPI)

• Number of channels: One (max.)

• Supports full-duplex operation

• Master/slave mode

• Selectable bit rate generated by the on-chip baud-rate generator

Multimedia card

interface (MMCIF)

• Number of channels: One (max.)

• Supports a subset of version 3.1 of the multimedia card system

specification

• Supports MMC-mode operation

• Interfaces with MMCCLK output (transfer clock output), MMCCMD I/O

(command output/response input), and MMCDAT I/O (data I/O) pins

Audio codec

interface (HAC)

• Number of channels: Two (max.)

• Digital interface for audio codecs

• Supports transfer via slots 1 to 4

• Choice of 16- or 20-bit DMA transfer rates for transmission/reception

• Supports various sampling rates by adjusting the allocation of data to

slots

SH7785 Datasheet(PDF) 41 Page - Renesas Technology Corp

SH7785 Datasheet(HTML) 41 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL