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SH7785 Datasheet(PDF) 178 Page - Renesas Technology Corp |
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SH7785 Datasheet(HTML) 178 Page - Renesas Technology Corp |
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178 / 1692 page ![]() 7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 148 of 1658 REJ09B0261-0100 (b) P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address. Whether or not the cache is used is determined by the CCR setting. When the cache is used, switching between the copy-back method and the write-through method for write accesses is specified by the CB bit in CCR. (c) P2 Area The P2 area does not allow address translation using the TLB and access using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address. (d) P4 Area The P4 area is mapped onto the internal resource of this LSI. This area except the store queue and on-chip memory areas does not allow address translation using the TLB. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 7.4. H'E000 0000 H'E400 0000 H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000 H'FC00 0000 H'FFFF FFFF Store queue Reserved area Reserved area On-chip memory area Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data array Operand cache address array Operand cache data array Unified TLB and PMB address array Unified TLB and PMB data array Reserved area Control register area H'E500 0000 H'E600 0000 Figure 7.4 P4 Area |
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