32186 datasheet(575/1032 Pages) RENESAS

575 / 1032 page

SERIAL INTERFACE

12-27

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.2.8 SIO Special Mode Registers

SIO0 Special Mode Register (S0SMOD)

<Address: H'0080 0118>

SIO1 Special Mode Register (S1SMOD)

<Address: H'0080 0128>

SIO2 Special Mode Register (S2SMOD)

<Address: H'0080 0138>

SIO3 Special Mode Register (S3SMOD)

<Address: H'0080 0148>

SIO4 Special Mode Register (S4SMOD)

<Address: H'0080 0A18>

SIO5 Special Mode Register (S5SMOD)

<Address: H'0080 0A28>

123456

CKPOL

00000000

SEL3PNT

SELFST

SELCLK

CSIBL

Bit Name

Function

0–3

CSIBL

0000: 8 bits

CSIO bit length select bit

0001: 9 bits

0010: 10 bits

0011: 11 bits

0100: 12 bits

0101: 13 bits

0110: 14 bits

0111: 15 bits

1xxx: 16 bits

SELCLK

0: f(BCLK)/2

Clock divider count source select bit

1: f(BCLK)

SELFST

0: LSB-first

Transfer order select bit

1: MSB-first

SEL3PNT

0: 3-point sampling invalid

3-point sampling control bit

1: 3-point sampling valid

CKPOL

0: Transmit data output at SCLK falling edge

Transmit/receive clock polarity select bit

Receive data fetch at SCLK rising edge

1: Transmit data output at SCLK rising edge

Receive data fetch at SCLK falling edge

(1) CSIBL (CSIO Bit Length Select) bits (Bits 0–3)

These bits are effective only when the clock-synchronous serial interface was selected with the trans-

mitting/receiving mode register. They select the data length.

(2) SELCLK (Clock Divider Count Source Select) bit (Bit 4)

This bit is provided for selection of clock divider count source.

(3) SELFST (Transfer Order Select) bit (Bit 5)

This bit selects the data bit transfer order.

(4) SEL3PNT (3 Points Sampling Control) bit (Bit 6)

Setting this bit to “1” allows 3-point sampling of each signal of RxD input/SCLKI input with BCLK

period, and SIO operates with its majority output as RxD input/SCLKI input. RxD input and SCLKI

input cannot be controlled individually. Also, 3-point sampling for SCLKI becomes effective only at

CSIO mode and external clock selection.

12.2 Serial Interface Related Registers

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