32186 datasheet(577/1032 Pages) RENESAS

577 / 1032 page

SERIAL INTERFACE

12-29

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.3 Transmit Operation in CSIO Mode

12.3.1 Setting CSIO Baud Rate

The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock

source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or

external clock. The CKS (Internal/External Clock Select) bit (SIO Transmit/Receive Mode Register bit 11)

is used to select the clock source.

The equation used to calculate the transmit/receive baud rate differs depending on whether an internal or

external clock is selected.

(1) When internal clock is selected in CSIO mode

When the internal clock was selected, select the clock source from f(BCLK) or f(BCLK)/2 with the

clock divider count source select bit (bit 4 of SIO special mode register). f(BCLK) or f(BCLK)/2 is input

to the baud rate generator (BRG) after being divided by the clock divider.

The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the CDIV (baud rate

generator count source select) bits (Transmit Control Register bits 2–3).

The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and

further by 2, thus generating a transmit/receive shift clock.

When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below.

Baud rate =

f(BCLK) or f(BCLK)/2

[bps]

Clock divider’s divide-by value x (baud rate register set value + 1) x 2

Baud rate register set value = H’00 to H’FF (Note 1)

Clock divider’s divide-by value = 1, 8, 32 or 256

Note 1: Use caution when setting the baud rate register so that the transfer rate does not exceed f(BCLK)/8.

(2) When external clock is selected in CSIO mode

In this case, the Baud Rate Generator is not used, and the input clock from the SCLKI pin serves

directly as a transmit/receive shift clock for CSIO.

The maximum frequency of the SCLKI pin input clock is f(BCLK)/16.

Baud rate = SCLKI pin input clock

[bps]

12.3 Transmit Operation in CSIO Mode

32186 Datasheet(PDF) 577 Page - Renesas Technology Corp