32186 datasheet(804/1032 Pages) RENESAS

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NON-BREAK DEBUG (NBD)

16-6

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

16.3 NBD Related Registers

The following shows an NBD related register map. Some NBD-related registers are located in the address map

(CPU space), and others are located in another area that is used exclusively for NBD (i.e., NBD space). The

NBD space is addressed by 12 bits, and is accessed in a fixed size of 8 bits. Furthermore, the NBD space is

constructed to be accessible from only the dedicated NBD interface, and cannot be accessed from the CPU.

Table 16.3.1 NBD Related Register Map

Space

Address

R/W

Upon exiting reset

CPU

H'E000 0000

NBD enable register (NBDENB)

R/W

H'00

H'E000 0004

NBD pin control register (NBDCNT)

R/W

H'00

H'E000 0008

Event generation register (NEVNTGEN)

Indefined

NBD

H'800

Event address setting register (EVTU_A)

R/W

Indefined

H'801

H'802

H'803

H'820

Event condition setting register (EVTU_C)

R/W

Indefined

16.3.1 NBD Enable Register

NBD Enable Register (NBDENB)

<Address: H'E000 0000>

123456

NBDENP

NBDEN

Bit Name

Function

0–5

No function assigned. Fix to "0."

NBDENP

NBDEN write control bit

NBDEN

0: Disable NBD operation

NBD operation enable bit

1: Enable NBD operation

Notes: • Allow for an interval time of 20 CPUCLK cycles or more before altering the value of the NBDEN bit.

• If the NBDEN bit is reenabled after being disabled, a finite time of 20 CPUCLK cycles is required before the NBD becomes operational.

• The value of the NBDEN bit can only be altered when the NBDSET bit in the NBD Pin Control Register = "0" (NBD-related

pins set for other than the NBD function).

The NBDEN bit selects to enable or disable the NBD functions. When NBDEN = "0," the NBD is in a reset

state, so that the content of each register is reset to the initial value. To use the NBD functions, this bit

should be set to "1" before setting other NBD registers.

When the NBDEN bit = "0," accessing not just the NBDENB register, but any other NBD registers (in either

the CPU or the NBD space) is prohibited.

To set the register, follow the procedure described below.

1. Write a "1" to NBDENP bit.

2. Subsequent to 1 above, write a "0" to NBDENP bit and a "0" or "1" to NBDEN bit.

Notes: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and

2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled

and the writing value is not reflected. Therefore, disable interrupts and DMA transfers

before setting. However the writing cycle from RTD and DRI are not effected.

• The setting procedure of NBDEN bit is same as that of NBDSET bit shown in Figure 16.2.1.

16.3 NBD Related Registers

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