32186 datasheet(805/1032 Pages) RENESAS

805 / 1032 page

NON-BREAK DEBUG (NBD)

16-7

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 16.4.1 NBDD3–NBDD0 Input Format

NBDCLK

NBDSYNC#

NBDD3

–NBDD0

Write field (Only when writing)

n = 7,15 or 31

Extension

field

Control

field

Address field

Command packet

NBDD3

–NBDD0

Hi-Z

0000

SIZ1, SIZ0,

R/W, I/T

A28

–A31

–A3

Dn-3

–Dn

–D3

Note: •

:Sampling Point

Hi-Z

16.4 Communication Protocol

When NBDSYNC# is asserted, the NBD starts latching NBDD3–NBDD0 into the internal circuit synchro-

nously with NBDCLK. Make sure NBDD3–NBDD0 are input in the format shown below.

When data input from NBDD3–NBDD0 shown in Figure 16.4.1 finishes, the data bus is temporarily placed in

the high-impedance (Hi-Z) state for 1 NBDCLK cycle and then data is output from NBDD3–NBDD0 synchro-

nously with NBDCLK in the format shown in Figure 16.4.2.

Figure 16.4.2 NBDD3–NBDD0 Output Format

16.4 Communication Protocol

Flag sense

Read data packet (Only when reading)

n = 7,15 or 31

NBDSYNC#

NBDD3

–NBDD0

Dn-3

–Dn

NBDCLK

Note: •

:Sampling Point

Not Ready

Ready

Hi-Z

–D3

Hi-Z

0000

0001

32186 Datasheet(PDF) 805 Page - Renesas Technology Corp

32186 Datasheet(HTML) 805 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL