32186 datasheet(810/1032 Pages) RENESAS

810 / 1032 page

NON-BREAK DEBUG (NBD)

16-12

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

16.6.2 Event Condition Setting Register

Event Condition Setting Register (EVTU_C)

<Address: H'820 (NBD space)>

123456

ACC0

ACC1

00000??0

Bit Name

Function

0–4

No function assigned. Fix to "0."

5, 6

ACC1, ACC0

Specify R/W condition for event detection

ACC1 ACC0

Event generation condition

Read access

Write access

Read or write access

Settings inhibited

No function assigned. Fix to "0."

Notes: • In the NBDEN bit of NBD enable register (NBDENB), AVTU_A bit value becomes indefinite after setting from "0" (disable

NBD operation) to "1"(enable NBD operation).

• After e bling NBD operation(after setting "1"in NBDEN bit of NBDENB register), an indefinite value is outputted from

NBDEVENT# pin in NBD pin control register(NBDCNT) during the period of time from setting NBD-related pins to NBD

function to setting value of EVTU_A and EVTU_C are effective(period of time from Ready status to after 3NBDCLK).

• During event detection function is used, when the setting value of EVTU_A register or EVTU_C register is changed, the

event detection result by the changed setting conditions becomes effective after 3NBDCLK from setting EVTU_A

For executed-PC event detection can be implemented using the Event Address set registter (EVTU_A)

and the Event Condition set registter (EVTU_C), it is necessary that the target PC address be set in the

EVTU_A register and that the ACC1 and ACC0 bits of the EVTU_C register be set to ‘H'00’ (read ac-

cess). Once these settings are made, when the EVTU_A register address is accessed for instruction

read (instruction prefetch) by the CPU, event output can be generated upon detecting this CPU access.

In this case, event can also be generated for an operand access to the EVTU_A register address by the

CPU. Note that since this facility is designed to detect an event occurrence for instruction read access

(instruction prefetch), events may be generated for instructions that actually are not executed.

16.6.3 Event Generation Register

Event Generation Register (NEVNTGEN)

<Address: H'E000 0008>

123456

NEVNTGEN

????????

Bit Name

Function

0–7

NEVNTGEN

When any data is written to this register, "L" level signal is

–

output from the NBDEVNT# pin for 2 BCLK cycles. When this

Note: • If multiple events occur in close proximity in time, "L" level signal output from the NBDEVNT# pin may only be asserted

"L" for 2 BCLK cycles (i.e., for one event). Conversely, depending on event occurrence conditions, two or more 2-BCLK

"L" level signals may be output in succession.

16.6 Event Detection Function

Figure 16.6.2 Relationship between NBD Event Detection and NBDEVENT# Pin Operation

BCLK

NBD event detection

NBDEVNT# output

For one event detected,

asserted "L" for 2 BCLK

cycles (for one event)

For two events detected,

asserted "L" for 2 BCLK

cycles (for one event)

Asserted "L"

consecutively

for 4 BCLK cycles

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