32186 datasheet(814/1032 Pages) RENESAS

814 / 1032 page

EXTERNAL BUS INTERFACE

17-4

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(10) Peripheral clock (BCLK)

The peripheral clock is output from the pin. If the CPU clock is 80 MHz, a 20 MHz clock is output. Further-

more, if the BCLK output function is unused, and P70MD in the P7 Operation Mode Register is cleared to

“0,” the pin can be used as P70.

Note: • During external extension mode, this pin is switched for port upon exiting reset. Its pin function must

be set for peripheral clock using the corresponding Port Operation Mode Register and Port Periph-

eral Function Select Register as necessary.

The status of each pin during hold are shown below.

Table 17.1.1 Pin State during Hold Period

Pin Name

Pin State or Operation

A9–A30, DB0–DB15, CS0#–CS3#, RD#, BHW#, BLW#, BHE#, BLE#, WR#

High impedance

HACK#

Output "L"

Other pins (e.g., ports and timer output)

Normal operation

(11) Bus power supply (VCC-BUS)

This pin supplies power to the bus control pins. A voltage different from that of the main power supply can be

applied, which is convenient when external devices are connected to the system.

17.1 Outline of External Bus Interface

32186 Datasheet(PDF) 814 Page - Renesas Technology Corp