32186 datasheet(999/1032 Pages) RENESAS

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SUMMARY OF PRECAUTIONS

Appendix 4

Appendix 4-9

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Appendix 4.9 Notes on Multijunction Timers

Appendix 4.9.2 Notes on using TOP delayed single-shot output mode

The following describes precautions to be observed when using TOP delayed single-shot output mode.

• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the

former has priority so that the counter stops.

• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable

bit, the latter has priority so that count is enabled.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable

bit, the latter has priority so that count is disabled.

• Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an

overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt

request is generated for an underflow that includes the overflowed count.

• If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes

to "reload register value -1" at the next count clock timing after underflow.

Appendix Figure 4.9.2 Counter Value Immediately after Underflow

Count clock

Enable bit

"H"

H'0001

H'0000

H'FFFF

H'AAA9

H'AAA8

Counter value

H'AAAA

Reload register

underflow

H'(AAAA-1)

H'(AAAA-2)

What is seen during underflow cycle is always H'FFFF,

and not the reload register value (in this case, H'AAAA).

Count down from the

reload register value

Reload cycle

The value that "reload register - 1" is reloaded

by count clock next underflow

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