HD64F7047 datasheet(152/764 Pages) RENESAS

152 / 764 page

Rev. 2.00, 09/04, page 112 of 720

8.2.1

DTC Mode Register (DTMR)

DTMR is a 16-bit register that selects the DTC operating mode.

Bit

Bit Name

Initial

Value

R/W

Description

SM1

SM0

Undefined



Source Address Mode 1 and 0

These bits specify a DTSAR operation after a data

transfer.

0x: DTSAR is fixed

10: DTSAR is incremented after a transfer

(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1

and 0 = 01; by +4 when Sz 1 and 0 = 10)

11: DTSAR is decremented after a transfer

(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1

and 0 = 01; by –4 when Sz 1 and 0 = 10)

DM1

DM0

Undefined



Destination Address Mode 1 and 0

These bits specify a DTDAR operation after a data

transfer.

0x: DTDAR is fixed

10: DTDAR is incremented after a transfer

(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1

and 0 = 01; by +4 when Sz 1 and 0 = 10)

11: DTDAR is decremented after a transfer

(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1

and 0 = 01; by –4 when Sz 1 and 0 = 10)

MD1

MD0

Undefined



DTC Mode 1 and 0

These bits specify the DTC transfer mode.

00: Normal mode

01: Repeat mode

10: Block transfer mode

11: Setting prohibited

Sz1

Sz0

Undefined



DTC Data Transfer Size 1 and 0

Specify the size of data to be transferred.

00: Byte-size transfer

01: Word-size transfer

10: longword-size transfer

11: Setting prohibited

HD64F7047 Datasheet(PDF) 152 Page - Renesas Technology Corp

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