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HD64F7047 Datasheet(PDF) 153 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 153 Page - Renesas Technology Corp |
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153 / 764 page ![]() Rev. 2.00, 09/04, page 113 of 720 Bit Bit Name Initial Value R/W Description 7 DTS Undefined DTC Transfer Mode Select Specifies whether the source or the destination is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination is repeat area or block area 1: Source is repeat area or block area 6 CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. 0: Chain transfer is canceled 1: Chain transfer is set In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTER is not performed. 5 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated for every DTC transfer. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 4 NMIM Undefined DTC NMI Mode This bit designates whether to terminate transfers when an NMI is input during DTC transfers. 0: Terminate DTC transfer upon an NMI 1: Continue DTC transfer until end of transfer being executed 3 to 0 Undefined Reserved These bits have no effect on DTC operation and should always be written with 0. [Legend] X: Don’t care |
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