HD64F7047 datasheet(166/764 Pages) RENESAS

Part #	HD64F7047

Description	Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

PDF	764 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

166 / 764 page

Rev. 2.00, 09/04, page 126 of 720

Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed

consecutively in a single activation source. DTSAR, DTDAR, DTMR, DTCRA, and DTCRB can

be set independently.

Figure 8.9 shows the chain transfer.

When activated, the DTC reads the register information start address stored at the vector address,

and then reads the first register information at that start address. After the data transfer, the CHNE

bit will be tested. When it has been set to 1, DTC reads next register information located in a

consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit

is cleared to 0.

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

DTC vector

address

Source

Destination

Source

Destination

CHNE = 1

CHNE = 0

start address

Figure 8.9 Chain Transfer

HD64F7047 Datasheet(PDF) 166 Page - Renesas Technology Corp