HD64F7047 datasheet(167/764 Pages) RENESAS

167 / 764 page

Rev. 2.00, 09/04, page 127 of 720

8.3.4

Interrupt Source

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers

have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

Note:

When the DTCR contains a value equal to or greater than 2, the SWDTE bit is

automatically cleared to 0. When the DTCR is set to 1, the SWDTE bit is again set to 1.

8.3.5

Operation Timing

When register information is located in on-chip RAM, each mode requires 4 cycles for transfer

information reads, and 3 cycles for writes.

Activating

source

Address

Vector

read

Transfer information

read

Data

transfer

Transfer

information write

DTC

request

Figure 8.10 DTC Operation Timing Example (Normal Mode)

HD64F7047 Datasheet(PDF) 167 Page - Renesas Technology Corp