4501 datasheet(36/212 Pages) RENESAS

36 / 212 page

FUNCTION BLOCK OPERATIONS

1-24

Rev.2.01

Feb 07, 2005

4501 Group

HARDWARE

REJ09B0192-0201

(2) External interrupt control registers

• Interrupt control register I1

rupt. Set the contents of this register through register A with the

TI1A instruction. The TAI1 instruction can be used to transfer the

contents of register I1 to register A.

Table 8 External interrupt control register

I13

I12

I11

I10

INT pin input control bit (Note 2)

Interrupt valid waveform for INT pin/

return level selection bit (Note 2)

INT pin edge detection circuit control bit

INT pin

timer 1 control enable bit

Interrupt control register I1

R/W

at RAM back-up : state retained

at reset : 00002

INT pin input disabled

INT pin input enabled

Falling waveform (“L” level of INT pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-

struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

performed with the SNZ0 instruction.

4501 Datasheet(PDF) 36 Page - Renesas Technology Corp