4501 datasheet(62/212 Pages) RENESAS

62 / 212 page

1-50

Rev.2.01

Feb 07, 2005

4501 Group

HARDWARE

REJ09B0192-0201

LIST OF PRECAUTIONS

➀ Noise and latch-up prevention

Connect a capacitor on the following condition to prevent noise

and latch-up;

• connect a bypass capacitor (approx. 0.1

µF) between pins VDD

and VSS at the shortest distance,

• equalize its wiring in width and length, and

• use relatively thick wire.

In the One Time PROM version, CNVSS pin is also used as VPP

pin. Accordingly, when using this pin, connect this pin to VSS

through a resistor about 5 k

Ω (connect this resistor to CNVSS/

VPP pin as close as possible).

➁ Register initial values 1

The initial value of the following registers are undefined after sys-

tem is released from reset. After system is released from reset,

set initial values.

• Register Z (2 bits)

• Register D (3 bits)

• Register E (8 bits)

➂ Register initial values 2

The initial value of the following registers are undefined at RAM

back-up. After system is returned from RAM back-up, set initial

values.

• Register Z (2 bits)

• Register X (4 bits)

• Register Y (4 bits)

• Register D (3 bits)

• Register E (8 bits)

➃ Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are eight identical registers, so that subrou-

tines can be nested up to 8 levels. However, one of stack

registers is used respectively when using an interrupt service

routine and when executing a table reference instruction. Accord-

ingly, be careful not to over the stack when performing these

operations together.

➄ Prescaler

Stop the prescaler operation to change its frequency dividing ra-

tio.

➅Timer count source

Stop timer 1 or 2 counting to change its count source.

➆ Reading the count value

Stop timer 1 or 2 counting and then execute the TAB1 or TAB2

instruction to read its data.

➇ Writing to the timer

Stop timer 1 or 2 counting and then execute the T1AB or T2AB

instruction to write its data.

➈ Writing to reload register R1

When writing data to reload register R1 while timer 1 is operat-

ing, avoid a timing when timer 1 underflows.

Watchdog timer

• The watchdog timer function is valid after system is released

from reset. When not using the watchdog timer function, execute

the DWDT instruction and the WRST instruction continuously,

and clear the WEF flag to “0” to stop the watchdog timer function.

• The watchdog timer function is valid after system is returned from

the RAM back-up. When not using the watchdog timer function,

execute the DWDT instruction and the WRST instruction continu-

ously every system is returned from the RAM back-up, and stop

the watchdog timer function.

Multifunction

• The input/output of D2, D3, P12 and P13 can be used even when

C, K, CNTR (input) and INT are selected.

• The input of P12 can be used even when CNTR (output) is selected.

• The input/output of P20 and P21 can be used even when AIN0 and

AIN1 are selected.

Program counter

Make sure that the PCH does not specify after the last page of

the built-in ROM.

POF and POF2 instructions

When the POF or POF2 instruction is executed continuously af-

ter the EPOF instruction, system enters the RAM back-up state.

Note that system cannot enter the RAM back-up state when ex-

ecuting only the POF or POF2 instruction.

Be sure to disable interrupts by executing the DI instruction be-

fore executing the EPOF instruction and the POF or POF2

instruction continuously.

LIST OF PRECAUTIONS

Timer 1 and timer 2 count start timing and count time when

operation starts

Count starts from the first rising edge of the count source (2) af-

ter timer 1 and timer 2 operations start (1).

Time to first underflow (3) is shorter (for up to 1 period of the

count source) than time among next underflow (4) by the timing

to start the timer and count source operations after count starts.

When selecting CNTR input as the count source of timer 2, timer

2 operates synchronizing with the falling edge of CNTR input.

Fig. 48 Timer count start timing and count time when opera-

tion starts (T1, T2)

(1) Timer

Count Source

Timer Value

Timer Underflow

Signal

032

103

Count Source

(CNTR input)

(2)

(3)

(4)

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