7906 datasheet(187/531 Pages) RENESAS

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PULSE OUTPUT PORT MODE

7906 Group User’s Manual Rev.2.0

9-6

9.2 Block description

9.2.2 Three-phase output data registers 0, 1

Figure 9.2.3 shows the structures of three-phase output data registers 0, 1 (in the pulse output port mode).

Fig. 9.2.3 Structures of three-phase output data registers 0, 1 (in pulse output port mode)

7, 6

Bit name

Bit

Three-phase output data register 0 (Address A816)

Function

At reset

R/W

b7 b6 b5 b4 b3 b2 b1 b0

0 : “L” level output

1 : “H” level output

Note: Invalid in pulse mode 0.

RTP00 pulse output data bit

RTP01 pulse output data bit

RTP02 pulse output data bit

RTP03 pulse output data bit

RTP10 pulse output data bit

(Valid in pulse mode 1.) (Note)

RTP11 pulse output data bit

(Valid in pulse mode 1.) (Note)

Pulse output trigger select bits

0 : “L” level output

1 : “H” level output

0 0 : Underflow of timer A0

0 1 : Falling edge of input signal to pin RTPTRG0

1 0 : Rising edge of input signal to pin RTPTRG0

1 1 : Both falling and rising edges of input signal to

pin RTPTRG0

b7 b6

Three-phase output data register 1 (Address A916)

Pulse width modulation enable

bit 0

Pulse width modulation enable

bit 1

Pulse width modulation enable

bit 2

Pulse output polarity select bit

RTP10 pulse output data bit

(Valid in pulse mode 0) (Note)

RTP11 pulse output data bit

(Valid in pulse mode 0) (Note)

Bit name

Bit

Function

At reset

R/W

0 : Positive

1 : Negative

0 : No pulse width modulation by timer A1

1 : Pulse width modulation by timer A1

b7 b6 b5 b4 b3 b2 b1 b0

0 : No pulse width modulation by timer A2

1 : Pulse width modulation by timer A2

0 : No pulse width modulation by timer A4

1 : Pulse width modulation by timer A4

0 : “L” level output

1 : “H” level output

X: It may be either “0” or “1.”

Note: Invalid in pulse mode 1.

Invalid in pulse output port mode.

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