M68HC08 datasheet(34/188 Pages) FREESCALE

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Memory

Data Sheet

MC68HC908RF2 — Rev. 4.0

Memory

MOTOROLA

2.5.5 FLASH 2TS Block Protection

NOTE:

In performing a program or erase operation, the FLASH 2TS block protect register

must be read after setting the PGM or ERASE bit and before asserting the HVEN

bit.

Due to the ability of the on-board charge pump to erase and program the FLASH

2TS memory in the target application, provision is made for protecting blocks of

memory from unintentional erase or program operations due to system

malfunction. This protection is implemented by a reserved location in the memory

for block protect information. This block protect register must be read before setting

HVEN = 1. When the block protect register is read, its contents are latched by the

FLASH 2TS control logic. If the address range for an erase or program operation

includes a protected block, the PGM or ERASE bit is cleared which prevents the

HVEN bit in the FLASH 2TS control register from being set such that no

high-voltage operation is allowed in the array.

When the block protect register is erased (all 0s), the entire memory is accessible

for program and erase. When bits within the register are programmed, they lock

blocks of memory address ranges as shown in 2.5.6 FLASH 2TS Block Protect

an external voltage VTST present on the IRQ pin. The presence of VTST on the IRQ

pin also allows entry into monitor mode out of reset. Therefore, the ability to change

the block protect register is voltage-level dependent and can occur in either user or

monitor modes.

2.5.6 FLASH 2TS Block Protect Register

The block protect register (FLBPR) is implemented as a byte within the FLASH 2TS

memory. Each bit, when programmed, protects a range of addresses in the FLASH

2TS.

BPR3 — Block Protect Register Bit 3

This bit protects the memory contents in the address ranges $7A00–$7FEF and

$FFF0–$FFFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

Address:

$FFF0

Bit 7

654321

Bit 0

Read:

RRRR

BPR3

BPR2

BPR1

BPR0

Write:

Reset:

Unaffected by reset

R= Reserved

Figure 2-5. FLASH 2TS Block Protect Register (FLBPR)

Freescale Semiconductor, Inc.

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