M68HC08 datasheet(44/188 Pages) FREESCALE

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Configuration Register (CONFIG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Configuration Register (CONFIG)

MOTOROLA

frequency higher (307.2 kHz–32 MHz) or lower (60 Hz–307.2 kHz) than the

base frequency of the internal oscillator. (See Section 6. Internal Clock

Generator Module (ICG).)

1 = ICG set for slow external crystal operation

0 = ICG set for fast external crystal operation

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWR bit is set, setting the LVISTOP bit enables the LVI to operate

during stop mode. Reset clears LVISTOP.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

LVIRST — LVI Reset Enable Bit

LVIRST enables the reset signal from the LVI module. (See Section 8.

Low-Voltage Inhibit (LVI).)

1 = LVI module resets enabled

0 = LVI module resets disabled

LVIPWR — LVI Power Enable Bit

LVIPWR disables the LVI module. (See Section 8. Low-Voltage Inhibit (LVI).)

1 = LVI module power enabled

0 = LVI module power disabled

COPRS — COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. (See Section 4.

Computer Operating Properly Module (COP).)

1 = COP timeout period = 213 – 24 CGMXCLK cycles

0 = COP timeout period = 218 – 24 CGMXCLK cycles

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles

instead of a 4096-CGMXCLK cycle delay.

1 = Stop mode recovery after 32 CGMXCLK cycles

0 = Stop mode recovery after 4096 CGMXCLK cycles

NOTE:

Exiting stop mode by pulling reset will result in the long stop recovery.

If using the internal clock generator module or an external crystal oscillator, do not

set the SSREC bit.

The LVI has an enable time of tEN. The system stabilization time for power-on reset

and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the

LVI enable time for these startup scenarios. There is no period where the MCU is

not protected from a low-power condition. However, when using the short stop

recovery configuration option, the 32 CGMXCLK delay must be greater than the

LVI’s turn on time to avoid a period in startup where the LVI is not protecting the

MCU.

Freescale Semiconductor, Inc.

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