M68HC08 datasheet(85/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Low-Power Modes

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

The method of changing the unadjusted operating point is by changing the size of

the capacitor. This capacitor is designed with 639 equally sized units, 384 of which

are always connected. The remaining 255 units are put in by adjusting the ICG trim

factor (TRIM). The default value for TRIM is $80, or 128 units, making the default

capacitor size 512. Each unit added or removed will adjust the output frequency by

about

±0.195 percent of the unadjusted frequency (adding to TRIM will decrease

frequency). Therefore, the frequency of IBASE can be changed to

±25 percent of

its unadjusted value, which is enough to cancel the process variability mentioned

before.

The best way to trim the internal clock is to use the timer to measure the width of

an input pulse on an input capture pin (this pulse must be supplied by the

application and should be as long or wide as possible). Considering the prescale

value of the timer and the theoretical (zero error) frequency of the bus (307.2 kHz

*N/4), the error can be calculated. This error, expressed as a percentage, can be

divided by 0.195 percent and the resultant factor added or subtracted from TRIM.

This process should be repeated to eliminate any residual error.

NOTE:

It is recommended that the user preserve a copy of the contents of the ICG trim

Address $7FEF is reserved for an optional factory-determined value. Consult with

a local Motorola representative for more information and availability of this option.

6.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby

modes.

6.5.1 Wait Mode

The ICG remains active in wait mode. If enabled, the ICG interrupt to the CPU can

bring the MCU out of wait mode.

In some applications, low-power consumption is desired in wait mode and a

high-frequency clock is not needed. In these applications, reduce power

consumption by either selecting a low-frequency external clock and turning the

internal clock generator off, or reducing the bus frequency by minimizing the ICG

multiplier factor (N) before executing the WAIT instruction.

6.5.2 Stop Mode

The ICG is disabled in stop mode. Upon execution of the STOP instruction, all ICG

activity will cease and the output clocks (CGMXCLK and CGMOUT) will be held

low. Power consumption will be minimal.

The STOP instruction does not affect the values in the ICG registers. Normal

execution will resume after the MCU exits stop mode.

Freescale Semiconductor, Inc.

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