M68HC08 datasheet(78/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

6.4.3 Clock Monitor Interrupts

The clock monitor circuit can be used to recover from perilous situations such as

crystal loss. To use the clock monitor effectively, these notes should be observed:

•

Enable the clock monitor and clock monitor interrupts.

•

The first statement in the clock monitor interrupt service routine should be a

read to the ICG control register (ICGCR) to verify that the clock monitor flag

(CMF) is set. This is also the first step in clearing the CMF bit.

•

Never use BSET or BCLR instructions on the ICGCR, as this may

inadvertently clear CMF. Only use the BRSET and BRCLR instructions to

check the CMF bit and not to check any other bits in the ICGCR.

•

When the clock monitor detects inactivity on the selected clock source

(defined by the CS bit of the ICG control register), the inactive clock is

deselected automatically and the remaining active clock is selected as the

source for CGMXCLK. The interrupt service routine can use the state of the

CS bit to check which clock is inactive.

•

When the clock monitor detects inactivity, the application may have been

subjected to extreme conditions which may have affected other circuits. The

clock monitor interrupt service routine should take any appropriate

precautions.

6.4.4 Quantization Error in DCO Output

The digitally controlled oscillator (DCO) is comprised of three major sub-blocks:

Binary weighted divider

Variable-delay ring oscillator

Ring oscillator fine-adjust circuit

Each of these blocks affects the clock period of the internal clock (ICLK). Since

these blocks are controlled by the digital loop filter (DLF) outputs DDIV and DSTG,

the output of the DCO can change only in quantized steps as the DLF increments

or decrements its output. The following sections describe how each block will affect

the output frequency.

6.4.4.1 Digitally Controlled Oscillator

The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates

the internal clock (ICLK), whose clock period is dependent on the digital loop filter

outputs (DSTG[7:0] and DDIV[3:0]). Because of the digital nature of the DCO, the

clock period of ICLK will change in quantized steps. This will create a clock period

difference or quantization error (Q-ERR) from one cycle to the next. Over several

cycles or for longer periods, this error is divided out until it reaches a minimum error

of 0.202 percent to 0.368 percent. The dependence of this error on the DDIV[3:0]

value and the number of cycles the error is measured over is shown in Table 6-3.

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