M68HC08 datasheet(88/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

6.7.1 ICG Control Register

The ICG control register (ICGCR) contains the control and status bits for the

internal clock generator, external clock generator, and clock monitor as well as the

clock select and interrupt enable bits.

CMIE — Clock Monitor Interrupt Enable Bit

This read/write bit enables clock monitor interrupts. An interrupt will occur when

both CMIE and CMF are set. CMIE can be set when the CMON bit has been set

for at least one cycle. CMIE is forced clear when CMON is clear or during reset.

1 = Clock monitor interrupts enabled

0 = Clock monitor interrupts disabled

CMF — Clock Monitor Interrupt Flag

This read-only bit is set when the clock monitor determines that either ICLK or

ECLK becomes inactive and the CMON bit is set. This bit is cleared by first

reading the bit while it is set, followed by writing the bit low. This bit is forced

clear when CMON is clear or during reset.

1 = Either ICLK or ECLK has become inactive.

0 = ICLK and ECLK have not become inactive since the last read of the

ICGCR or the clock monitor is disabled.

CMON — Clock Monitor On Bit

This read/write bit enables the clock monitor. CMON can be set when both ICLK

and ECLK have been on and stable for at least one bus cycle (ICGON, ECGON,

ICGS, and ECGS are all set). CMON is forced set when CMF is set, to avoid

inadvertent clearing of CMF. CMON is forced clear when either ICGON or

ECGON is clear or during reset.

1 = Clock monitor output enabled

0 = Clock monitor output disabled

Address: $0036

Bit 7

654321

Bit 0

Read:

CMIE

CMF

CMON

ICGON

ICGS

ECGON

ECGS

Write:

Reset:

00001000

= Unimplemented

Figure 6-11. ICG Control Register (ICGCR)

Freescale Semiconductor, Inc.

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