M68HC08 datasheet(69/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Functional Description

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

6.3.2.4 Digital Loop Filter

The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust

the internal clock (ICLK) clock period. The DLF generates the DCO divider control

bits (DDIV[3:0]) and the DCO stage control bits (DSTG[7:0]), which are fed to the

DCO. The DLF first concatenates the DDIV and DSTG registers

(DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the

relative error in the low-frequency base clock’s period, as shown in Table 6-1. In

some extreme error conditions, such as operating at a VDD level which is out of

specification, the DLF may attempt to use a value above the maximum ($9FF) or

below the minimum ($000). In both cases, the value for DDIV will be between $A

and $F. In this range, the DDIV value will be interpreted the same as $9 (the

slowest condition). Recovering from this condition requires subtracting (increasing

frequency) in the normal fashion until the value is again below $9FF (if the desired

value is $9xx, the value may settle at $Axx through $Fxx, an acceptable operating

condition). If the error is less than

±5 percent, the internal clock generator’s filter

stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock

monitor.

Table 6-1. Correction Sizes from DLF to DCO

Frequency Error

of IBASE Compared

to fNOM

DDVI[3:0]:DSTG[7:0]

Correction

Current to New

DDIV[3:0]:DSTG[7:0]

Relative Correction

in DCO

IBASE < 0.85 fNOM

–32 (–$020)

Min

$xFF to $xDF

–2/31

–6.45%

Max

$x20 to $x00

–2/19

–10.5%

0.85 fNOM < IBASE

IBASE < 0.95 fNOM

–8 (–$008)

Min

$xFF to $xF7

–0.5/31

–1.61%

Max

$x08 to $x00

–0.5/17.5

–2.86%

0.95 fNOM < IBASE

IBASE < fNOM

–1 (–$001)

Min

$xFF to $xFE

–0.0625/31

–0.202%

Max

$x01 to $x00

–0.0625/17.0625

–0.366%

fNOM < IBASE

IBASE < 1.05 fNOM

+1 (+$001)

Min

$xFE to $xFF

+0.0625/30.9375

+0.202%

Max

$x00 to $x01

+0.0625/17

+0.368%

1.05 fNOM < IBASE

IBASE < 1.15 fNOM

+8 (+$008)

Min

$xF7 to $xFF

+0.5/30.5

+1.64%

Max

$x00 to $x08

+0.5/17

+2.94%

1.15 fNOM < IBASE

+32 (+$020)

Min

$xDF to $xFF

+2/29

+6.90%

Max

$x00 to $x20

+2/17

+11.8%

x: Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]

carries or borrows.

Freescale Semiconductor, Inc.

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