M68HC08 datasheet(86/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

6.6 Configuration Register Option

One configuration register option affects the functionality of the ICG: EXTSLOW

(slow external clock).

All configuration register options will have a default setting. Refer to Section 3.

Configuration Register (CONFIG) on how the configuration register is used.

6.6.1 EXTSLOW

Slow external clock (EXTSLOW), when set, will decrease the drive strength of the

oscillator amplifier, enabling low-frequency crystal operation (30 kHz–100 kHz).

When clear, EXTSLOW enables high frequency crystal operation (1 MHz to

8MHz).

EXTSLOW, when set, also configures the clock monitor to expect an external clock

source that is slower than the low-frequency base clock (60 Hz–307.2 kHz). When

EXTSLOW is clear, the clock monitor will expect an external clock faster than the

low-frequency base clock (307.2 kHz–32 MHz).

The default state for this option is clear.

6.7 I/O Registers

The ICG contains five registers, summarized in Figure 6-10. These registers are:

•

ICG control register, ICGCR

•

ICG multiplier register, ICGMR

•

ICG trim register, ICGTR

•

ICG DCO divider control register, ICGDVR

•

ICG DCO stage control register, ICGDSR

Several of the bits in these registers have interaction where the state of one bit may

force another bit to a particular state or prevent another bit from being set or

cleared. A summary of this interaction is shown in Table 6-5.

Addr.

Bit 7

654321

Bit 0

$0036

Internal Clock Generator

Control Register (ICGCR)

See page 88.

Read:

CMIE

CMF

CMON

ICGON

ICGS

ECGON

ECGS

Write:

Reset:

00001000

$0037

Internal Clock Generator

Multiplier Register (ICGMR)

See page 90.

Read:

N6N5

N4N3N2N1N0

Write:

Reset:

00010101

Figure 6-10. ICG I/O Register Summary

Freescale Semiconductor, Inc.

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