TSC2117 datasheet(71/192 Pages) TI

71 / 192 page

5.7.1.2 Conversion Clock and Conversion Time

TSC2117

Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D

Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller

www.ti.com

SLAS550A – APRIL 2009 – REVISED JUNE 2009

Data Format

The TSC2117 output data is in unsigned binary format and can be read from two 8-bit registers over the

SPI interface.

Voltage Reference

The TSC2117 has an internal voltage reference that can be set to 1.25 V or 2.5 V through the reference

control register (page 3/regiser 6) .

The internal reference voltage should only be used in the single-ended mode for battery monitoring, for

temperature measurement, and for using the auxiliary inputs.

The TSC2117 is designed to allow use with an external voltage reference (page 3/regiser 6). In many

systems, a 2.5-V reference is supplied; however, this device supports a reference voltage up to the AVDD

level. The external reference should be a low-noise signal and accordingly, depending on the application,

it might be good to provide some R-C filtering at the VREF pin.

This voltage reference should only be used in the single-ended mode for measuring the auxiliary inputs

(AUX1, AUX2, and VBAT). Optimal touch-screen performance is achieved when using a ratiometric

conversion; thus, all touch-screen measurements are done automatically in the ratiometric mode.

Variable Resolution

The TSC2117 provides three different resolutions for the ADC: 8, 10, or 12 bits. Lower resolutions are

often practical for measurements such as system voltages. Performing the conversions at lower resolution

reduces the amount of time it takes for the ADC to complete its conversion process, which lowers power

consumption. The ADC resolution can be programmed by writing to page 3/register 2, bits D6–D5.

The TSC2117 contains an internal oscillator, which is used to drive the state machines inside the device

that perform the many functions of the part. MCLK is also available as a high-frequency clock source. The

clock source (internal or MCLK) is selected by writing to page 3/register 16, bit D7. This clock is divided

down to provide a clock to run the SAR ADC. The division ratio for this clock is set by writing to

page 3/register 2, bits D4–D3. The ability to change the conversion clock rate allows the user to choose

the optimal value for resolution, speed, and power. If the internal oscillator is used for the conversion

clock, the ADC is limited to 8-bit resolution; using higher resolutions at this speed does not result in

accurate conversions. Using a 4-MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution

requires that the conversion clock run at 1 or 2 MHz.

To avoid asynchronous issues, the system should use the same value for both page 3/register 16, bit 7

and page 3/register 17, bit 7.

Details for clock selection can be seen in Figure 5-40.

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TSC2117 Datasheet(PDF) 71 Page - Texas Instruments