TSC2117 datasheet(95/192 Pages) TI

95 / 192 page

5.9.1.3 I2S Mode

LD(n)

LD(n+1)

WORD

CLOCK

BIT

CLOCK

DATA

N N N

RD (n)

LEFT CHANNEL

RIGHT CHANNEL

LD(n)=n'thsampleofleftchanneldata

RD(n)=n'thsampleofrightchanneldata

LD(n)

LD (n+1)

WORD

CLOCK

BIT

CLOCK

DATA

RD(n)

LEFT CHANNEL

RIGHT CHANNEL

LD(n)=n'thsampleofleftchanneldata

RD(n)=n'thsampleofrightchanneldata

LD(n)

LD(n+1)

WORD

CLOCK

BIT

CLOCK

DATA

N N

RD(n)

LEFT CHANNEL

RIGHT CHANNEL

LD(n)=n'thsampleofleftchanneldata

RD(n)=n'thsampleofrightchanneldata

TSC2117

Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D

Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller

www.ti.com

SLAS550A – APRIL 2009 – REVISED JUNE 2009

The audio interface of the TSC2117 can be put into I2S mode by programming page 0/register 27, D(7:6)

= to 00. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after

the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising

edge of the bit clock after the rising edge of the word clock.

Figure 5-65. Timing Diagram for I2S Mode

Figure 5-66. Timing Diagram for I2S Mode with offset=2

Figure 5-67. Timing Diagram for I2S Mode with offset=0 and bit clock invert

For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed

word-length of the data. Also the programmed offset value should be less than the number of bit-clocks

per frame by at least the programmed word-length of the data.

Figure 5-68 shows the timing diagram for I2S mode for the monoaural audio ADC.

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