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TSC2117 Datasheet(PDF) 16 Page - Texas Instruments |
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TSC2117 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 192 page ![]() 3.4.6 SPI Interface Timing t td S ta MSB OUT BIT 6 . . . 1 LSB OUT t sck t Lead t Lag twsck t wsck tr tf tv tho tdis MSB IN BIT 6 . . . 1 LSB IN thi tsu SS SCLK MISO MOSI TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A – APRIL 2009 – REVISED JUNE 2009 www.ti.com All specifications at 25 °C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNITS MIN MAX MIN MAX twsck SCLK pulse duration 50 20 ns tLead Enable lead time 50 20 ns tLag Enable lag time 50 20 ns ttd Sequential transfer delay 40 20 ns ta MISO slave data-out access time 40 20 ns tdis MISO slave data-out disable time 40 20 ns tsu MOSI dataiin setup time 15 10 ns thi MOSI data-in hold time 15 10 ns tv MISO data-valid time 25 18 ns tr SCLK rise time 4 4 ns tf SCLK fall time 4 4 ns Figure 3-6. SPI Interface Timing Diagram ELECTRICAL SPECIFICATIONS 16 Submit Documentation Feedback |
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