TSC2117 datasheet(23/192 Pages) TI

23 / 192 page

5.2.1.2 Device Start-Up Lockout Times

5.2.1.3 PLL Start-Up

5.2.1.4 Power-Stage Reset

5.2.1.5 Software Power Down

5.2.2

Audio Analog I/O

5.3 miniDSP

TSC2117

Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D

Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller

www.ti.com

SLAS550A – APRIL 2009 – REVISED JUNE 2009

After the TSC2117 is initialized through hardware reset at power-up or software reset, the internal

memories are initialized to default values. This initialization takes place within 1 ms after pulling the

RESET signal high. During this initialization phase, no register-read or register-write operation should be

performed on ADC or DAC coefficient buffers. Also, no block within the codec should be powered up

during the initialization phase.

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up

command of the PLL and before the clocks are available to the codec. This delay is to ensure stable

operation of the PLL and clock-divider logic.

The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has

occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.

Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is

performed by setting page 1/register 31, bit D7 for HPL and by setting page 1/register 31, bit D6 for HPR.

The speaker power-stage reset is performed by setting page 1/register 32, bit D7 for SPLP and SPLN,

and by setting page 1/register 32, bit D6 for SPRP and SPRN.

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each

circuit block can be controlled by writing to the appropriate control register. This approach allows the

lowest power-supply current for the functionality required. However, when a block is powered down, all of

the register settings are maintained as long as power is still being applied to the device. The TSC2117

touch-detection circuitry is enabled by default, and it can be powered down by writing to page 3/register 4,

bit D7.

The TSC2117 has a stereo audio DAC and a monaural ADC. It supports a wide range of analog interfaces

to support different headsets and analog outputs. The TSC2117 has features to interface output drivers

(8-

Ω, 16-Ω, 32-Ω) and a microphone PGA with AGC control. A special circuit has also been included in

the TSC2117 to insert a short key-click sound into the stereo audio output. The key-click sound is used to

provide feedback to the user when a particular button is pressed or item is selected. The specific sound of

the keyclick can be adjusted by varying several register bits that control its frequency, duration, and

amplitude. See Key-Click Functionality With Beep Generator, Section 5.6.5

The TSC2117 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC; the

second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP

must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo

audio stream on the ADC and on the DAC side, offering the possibility for advanced, very low-group-delay

DSP algorithms.

The ADC miniDSP has 384 programmable instructions, 256 data memory locations, and 128

programmable coefficients. The DAC miniDSP has 1024 programmable instructions, 896 data memory

locations, and 512 programmable coefficients (in the adaptive mode, each bank has 256 programmable

coefficients).

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