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TSC2117 Datasheet(PDF) 13 Page - Texas Instruments |
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TSC2117 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 192 page ![]() 3.4.3 DSP Timing in Master Mode T0146-05 WCLK BCLK SDOUT SDIN t (DO-BCLK) d t (WS) d t (WS) d t (DI) S t (DI) h t f t r TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A – APRIL 2009 – REVISED JUNE 2009 All specifications at 25 °C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNITS MIN MAX MIN MAX td(WS) WCLK delay 45 20 ns td(DO-BCLK) BCLK to DOUT delay 45 20 ns ts(DI) SDIN setup 8 8 ns th(DI) SDIN hold 8 8 ns tr Rise time 25 10 ns tf Fall time 25 10 ns Figure 3-3. DSP Timing in Master Mode Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 13 |
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