ATmega32U2 datasheet(192/314 Pages) ATMEL

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192

7799B–AVR–07/09

ATmega8U2/16U2/32U2

20.5.3

Freeze clock

The firmware has the ability to freeze the clock of USB controller by setting the FRZCLK bit, and

thereby reduce the power consumption. When FRZCLK is set, it is still possible to access to the

following registers:

• USBCON

• DPRAM direct access registers (DPADD7:0, UEDATX)

•UDCON

•UDINT

•UDIEN

When FRZCLK is set, only the asynchronous interrupt may be triggered:

• WAKEUPI

20.6

Memory management

The controller does only support the following memory allocation management.

The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last

Endpoint). The firmware shall thus configure them in the same order.

The reservation of an Endpoint k

i is done when its ALLOC bit is set. Then, the hardware allo-

cates the memory and insert it between the Endpoints k

i-1 and ki+1. The ki+1 Endpoint memory

“slides” up and its data is lost. Note that the ki+2 and upper Endpoint memory does not slide.

Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration

(EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the

ki+1 Endpoint memory automatically slides down. Note that the ki+2 and upper Endpoint memory

does not slide.

The following figure illustrates the allocation and reorganization of the USB memory in a typical

example:

Table 20-1.

Allocation and reorganization USB memory flow

Free memory

EPEN=1

ALLOC=1

Free memory

EPEN=0

(ALLOC=1)

Free memory

Lost memory

Endpoints

activation

Endpoint Disable

Free its memory

(ALLOC=0)

Free memory

2 (bigger size)

Endpoint

Activatation

Conflict

ATmega32U2 Datasheet(PDF) 192 Page - ATMEL Corporation

ATmega32U2 Datasheet(HTML) 192 Page - ATMEL Corporation

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