PCIMX258CJM4A datasheet(41/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

Table 28 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.

Note:

1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs

model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.

4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,

I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).

Table 29 shows the AC requirements for DDR2 I/O.

Table 28. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O

Parameter

Symbol

Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units

Notes

Duty cycle

Fduty

—

Clock frequency

—

133

MHz

—

Output pad transition times

tpr

25 pF

50 pF

0.53/0.52

1.01/0.98

0.80/0.72

1.49/1.34

1.19/1.04

2.21/1.90

Output pad propagation delay, 50%–50%

input signals and crossing of output signals

tpo

25 pF

50 pF

1.3/1.21

1.59/1.5

1.97/1.84

2.37/2.24

2.91/2.71

3.48/3.28

Output pad propagation delay, 40%–60%

input signals and crossing of output signals

tpo

25 pF

50 pF

1.47/1.38

1.75/1.67

2.13/2.00

2.54/2.40

3.072/2.87

3.65/3.45

Output enable to output valid delay,

50%–50%

tpv

25 pF

50 pF

1.32/1.28

1.66/1.65

2.11/2.00

2.61/2.50

3.31/3.12

4.06/3.81

Output enable to output valid delay,

40%–60%

tpv

25 pF

50 pF

1.40/1.37

1.67/1.66

2.16/2.06

2.56/2.45

3.30/3.13

3.89/3.67

Output pad slew rate

tps

25 pF

50 pF

0.86/0.98

0.46/054

1.35/1.5

0.72/0.81

2.15/2.19

1.12/1.16

V/ns

Output pad dI/dt

tdit

25 pF

50 pF

172

183

400

422

mA/ns

Input pad transition times

trfi

1.0 pF

0.07/0.08

0.10/0.12

0.17/0.20

Input pad propagation delay, 50%–50%

tpi

1.0 pF

0.89/0.87

1.41/1.37

2.16/2.07

Input pad propagation delay, 40%–60%

tpi

1.0 pF

1.71/1.69

2.22/2.18

2.98/2.88

Table 29. AC Requirements for DDR2 I/O

Parameter1

1 Note that the Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any

specification in this document.

Symbol

Min.

Max.

Units

AC input logic high

VIH(ac)

OVDD/2 + 0.25

OVDD + 0.3

AC input logic low

VIL(ac)

–0.3

OVDD/2 – 0.25

AC differential input voltage2

Vid(ac)

0.5

OVDD + 0.6

AC differential cross point voltage for input3

Vix(ac)

OVDD/2–0.175

OVDD/2 + 0.175

AC differential cross point voltage for output4

Vox(ac)

OVDD/2–0.125

OVDD/2 + 0.125

PCIMX258CJM4A Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc

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