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PCIMX258CJM4A Datasheet(PDF) 99 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 99 Page - Freescale Semiconductor, Inc |
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99 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 99 Figure 71. SmartCard Interface Power Down AC Timing 3.7.15 System JTAG Controller (SJC) Timing Figure 72 through Figure 75 show respectively the test clock input, boundary scan, test access port, and TRST timings for the SJC. Table 76 describes the SJC timing parameters (SJ1–SJ13) indicated in the figures. Figure 72. Test Clock Input Timing Diagram Table 75. Timing Requirements for Power-down Sequence ID PARAMETER SYMBOL Min. Max. Unit SI7 SIM reset to SIM clock stop Srst2clk 0.9 × 1/Fckil 1.1 × 1/Fckil ns SI8 SIM reset to SIM Tx data low Srst2dat 1.8 × 1/Fckil 2.2 × 1/Fckil ns SI9 SIM reset to SIM voltage enable low Srst2ven 2.7 × 1/Fckil 3.3 × 1/Fckil ns SI10 SIM presence detect to SIM reset low Spd2rst 0.9 × 1/Fckil 1.1 × 1/Fckil ns SIMx_SIMPDy SIMx_RSTy SIMx_CLKy SIMx_RXy & SIMx_TXy SIMx_VENy SI7 SI8 SI9 SI10 TCK (Input) VM VM VIH VIL SJ1 SJ2 SJ2 SJ3 SJ3 |
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