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PCIMX258CJM4A Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 59 Figure 27. SDRAM Refresh Timing Diagram Table 43. SDR SDRAM Write Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns SD6 Address setup time tAS 2.0 — ns SD7 Address hold time tAH 1.8 — ns SD11 Precharge cycle period1 1 SD11 and SD12 are determined by SDRAM controller register settings. tRP 1 4 clock SD12 Active to read/write command delay1 tRCD 1 8 clock SD13 Data setup time tDS 2.0 — ns SD14 Data hold time tDH 1.3 — ns CS CAS WE RAS ADDR BA ROW/BA SD6 SD7 SD11 SD10 SD10 SDCLK SD1 SD2 SDCLK SD3 |
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